Digilent Parallel Interface Model Manuel d'utilisateur télécharger pdf (Page 11)

Digilent Parallel Interface Model Digilent, Inc.

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process (clkMain, regEppAdr, ctlEppDwr, busEppIn)

begin

if clkMain = '1' and clkMain'Event then

if ctlEppDwr = '1' and regEppAdr = "0101" then

regData5 <= busEppIn;

end if;

end process;

process (clkMain, regEppAdr, ctlEppDwr, busEppIn)

begin

if clkMain = '1' and clkMain'Event then

if ctlEppDwr = '1' and regEppAdr = "0110" then

regData6 <= busEppIn;

end if;

end process;

process (clkMain, regEppAdr, ctlEppDwr, busEppIn)

begin

if clkMain = '1' and clkMain'Event then

if ctlEppDwr = '1' and regEppAdr = "0111" then

regData7 <= busEppIn;

end if;

end process;

process (clkMain, regEppAdr, ctlEppDwr, busEppIn)

begin

if clkMain = '1' and clkMain'Event then

if ctlEppDwr = '1' and regEppAdr = "1010" then

regLed <= busEppIn;

end if;

end process;

------------------------------------------------------------------------

-- Gate array configuration verification logic

------------------------------------------------------------------------

-- This logic will flash the led on the gate array. This is to verify

-- that the gate array is properly configured for the test. This is a

-- simple way to verify that the gate array actually got configured.

led <= btn or cntr(23);

process (clkMain)

begin

if clkMain = '1' and clkMain'Event then

cntr <= cntr + 1;

end if;

end process;

----------------------------------------------------------------------------

end Behavioral;

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Digilent Parallel Interface Model Manuel d'utilisateur Page 11

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