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stEppNext <= stEppAwrB;

when stEppAwrB =>

if ctlEppAstb = '0' then

stEppNext <= stEppAwrB;

else

stEppNext <= stEppReady;

end if;

-- Read address register

when stEppArdA =>

stEppNext <= stEppArdB;

when stEppArdB =>

if ctlEppAstb = '0' then

stEppNext <= stEppArdB;

else

stEppNext <= stEppReady;

end if;

-- Write data register

when stEppDwrA =>

stEppNext <= stEppDwrB;

when stEppDwrB =>

if ctlEppDstb = '0' then

stEppNext <= stEppDwrB;

else

stEppNext <= stEppReady;

end if;

-- Read data register

when stEppDrdA =>

stEppNext <= stEppDrdB;

when stEppDrdB =>

if ctlEppDstb = '0' then

stEppNext <= stEppDrdB;

else

stEppNext <= stEppReady;

end if;

-- Some unknown state

when others =>

stEppNext <= stEppReady;

end case;

end process;

------------------------------------------------------------------------

-- EPP Address register

------------------------------------------------------------------------

process (clkMain, ctlEppAwr)

begin

if clkMain = '1' and clkMain'Event then

if ctlEppAwr = '1' then

regEppAdr <= busEppIn(3 downto 0);

end if;

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Digilent Parallel Interface Model Manuel d'utilisateur Page 9

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